1. Field of the Invention
The present invention relates to noise elimination circuits and, particularly, to a noise elimination circuit for eliminating the noise inputted immediately after a change in the logic level of an input signal to an integrated circuit.
2. Description of Related Art
In some cases, a narrow-width pulse inputted to an integrated circuit immediately after a change in the logic level of an input signal causes malfunction of the circuit. This noise is switching noise which occurs upon switching of the outputs of an output buffer circuit which sends the input signal or ringing noise. To eliminate such noise, some circuits have a delay circuit with a noise elimination function. These circuits compare the signal having passed through the delay circuit with an original signal, thereby outputting a signal with no noise.
FIG. 5 is a circuit diagram to explain a noise elimination circuit described in Japanese Unexamined Patent Publication No. 06-216723 (Yoshimitsuya et al.). This noise elimination circuit includes a delay circuit, PMOS transistors P1 and P2, NMOS transistors N3 and N4, and a latch circuit. The delay circuit includes inverters 5, 6, and a capacitor C1. The PMOS transistors P1 and P2 are connected in series between a power supply (VDD) and a node d. The NMOS transistors N3 and N4 are connected in series between the node d and a ground (GND). The latch circuit includes inverters 7, 8 and is connected to the node d. An input signal IN is inputted through a node a to the gates of the PMOS transistor P1 and the NMOS transistor N4 and also to the delay circuit, where it is delayed and then inputted to the gates of the PMOS transistor P2 and the NMOS transistor N3. An output signal OUT is outputted through the node d.
FIG. 6 is a timing chart to explain the operation of the noise elimination circuit. It shows a change in voltage at each node. The circuit operation is explained hereinafter with reference to FIG. 6. In the following description, a low logic level of a signal is referred to as “L”, and a high logic level as “H”. In the time period T1, the signal at the nodes a, b, and c, are “H”, “L”, and “H”, respectively. The PMOS transistors P1 and P2 are both off, and the NMOS transistors N3 and N4 are both on. The signal at the node d is thus “L”.
In T2, when the node a changes from “H” to “L”, the voltage at the node b increases from “L” to “H” due to the on-resistance of the inverter 5 in the “H” output state and the time constant of the capacitor C1. If the voltage at the node b reaches a logic threshold voltage of the inverter 6, the node c changes from “H” to “L”. Since the node a is “L” and the node c is “H” in T2, the PMOS transistor P2 and the NMOS transistor N4 are off. Though the node d thereby becomes in the high impedance state, it remains “L” because of the latch circuit including the inverters 7 and 8.
In T3, the nodes a and c turn to “L”. The PMOS transistors P1 and P2 are both on, and the NMOS transistors N3 and N4 are both off. The signal at the node d is thus “H”.
In T4, when the node a changes from “L” to “H”, the voltage at the node b decreases from “H” to “L” due to the on-resistance of the inverter 5 in the “L” output state and the time constant of the capacitor C1. If the voltage at the node b reaches the logic threshold voltage of the inverter 6, the node c changes from “L” to “H”. Since the node a is “H” and the node c is “L” in T4, the PMOS transistor P1 and the NMOS transistor N3 are off. Though the node d thereby becomes in the high impedance state, it remains “H” because of the latch circuit including the inverters 7 and 8. The operation in T5 is the same as that in T1, and the signal at the node d is “L”.
As described above, the signal transmission from the node a to the node d is blocked in T2 to T4. It is thereby possible to eliminate a narrow-width noise inputted in these time periods. The time periods T2 and T4 correspond, respectively, to a delay time Td of the delay circuit when the input changes from “H” to “L” and a delay time Td′ of the delay circuit when the input changes from “L” to “H”.
Yoshimitsuya et al. also teaches a delay circuit including a transistor and a capacitor so as to prevent malfunction due to the sequential input of a plurality of narrow-width noises. Further, Japanese Unexamined Patent Publication No. 10-294652 (Abe) discloses a noise elimination circuit which sets an optimum delay time for each of upward noise and downward noise.
It has now been discovered that the noise elimination circuits taught by Yoshimitsuya et al. and Abe have the problem that a delay time from the input of an input signal to the output of an output signal increases. This is because the circuits compare the signal having passed through the noise elimination circuit with the original signal to determine the output. For example, in the circuit taught by Yoshimitsuya et al., the delay circuit including the inverters 5, 6, and the capacitor C1 serves as a noise elimination circuit, and it determines the output by comparing the signal at the node c having passed through the noise elimination circuit with the original signal at the node a. Thus, the delay times Td and Td′ shown in FIG. 6 occur between the input of the input signal IN and the output of the output signal OUT.